One of the primary goals of memory manufacturers is increasing the storage density of memory devices. Improvements in integrated circuit fabrication techniques can achieve this goal by reducing the sizes of integrated circuit structures. Accordingly, as fabrication techniques improve, manufacturers can often increase memory densities simply by making the same memory structures smaller. Another technique for improving storage density is improving the functionality of memory structures to provide more storage per area. This can be achieved, for example, by creating memory cells and peripheral memory circuits that are capable of storing more information per memory cell.
U.S. Pat. No. 6,011,725, entitled xe2x80x9cTwo Bit Non-Volatile Electrically Erasable and Programmable Semiconductor Memory Cell Utilizing Asymmetrical Charge Trappingxe2x80x9d describes a non-volatile memory that stores two bits per memory cell. FIG. 1 shows a memory cell 100 such as described in U.S. Pat. No. 6,011,725. Memory cell 100 includes diffused N+ source/drain regions 120A and 120B in a silicon substrate 110, a gate insulator 130 overlying substrate 110, and a gate 150 overlying gate insulator 130. Gate insulator 130 has an ONO structure including a silicon nitride region 140 sandwiched between silicon dioxide regions 132 and 134.
Two bits of data are stored in memory cell 100 as charge that is trapped in separated and isolated locations 140A and 140B in nitride region 140. Each location 140A or 140B corresponds to a bit having a value 0 or 1 according to the state of trapped charge at the location 140A or 140B. To program cell 100, gate 150 is raised to a high voltage while a channel current passes between diffused regions 120A and 120B and injects charge into nitride region 140. The location 140A or 140B of the injected charge depends on the characteristics of memory cell 100, the applied voltages, and whether the channel current flows from region 120A to region 120B or from region 120B to region 120A. The direction of the channel current during a programming operation thus selects which of the bits (i.e., location 140A or 140B) is programmed.
Reading a data bit from a particular location 140A or 140B is accomplished by biasing gate 150 at a voltage that is above the threshold voltage of memory cell 100 when locations 140A and 140B are in an unprogrammed state. The diffused region 120A or 120B that is closest to the location 140A or 140B being read is biased as the source/region for the read operation. Any charge trapped in locations 140A and 140B affects a portion of the underlying channel so that negative charge trapped near the source effectively reduces the gate-to-source voltage and correspondingly reduces the channel current during the read operation. In contrast, negative charge near the drain region is ineffective at reducing the channel current since an appropriate drain voltage effectively punches through the portion of the channel near the drain. Sensing whether a channel current flows in memory cell 100 during the read indicates the value of the bit associated with the location 140A or 140B nearest the source/region 120A or 120B.
Memory cell 100 has the advantage of providing non-volatile storage of two bits of information in a single-transistor memory cell, increasing the storage density when compared to a memory device storing one bit of data per storage transistor. However, scaling memory cell 100 down to smaller feature sizes may present difficulties. In particular, operation of memory cell 100 requires the ability to inject charge into separate locations 140A and 140B in nitride region 140. As the size of nitride region 140 decreases, the shorter distance between locations 140A and 140B may be unable to accommodate lateral charge movement after the write operation. Additionally, the amount of charge trapped at locations 140A and 140B of nitride region 140 is relatively small (e.g., typically a few hundred electrons) when compared, for example, to the charge (e.g., typically tens of thousands of electrons) in the floating gate of a conventional Flash memory cell. The smaller trapped charge makes precise control of threshold voltages more difficult because small variations in the trapped charge have large effects. This renders analog or multi-bit storage at each location 140A or 140B in memory cell 100 substantially more difficult than analog or multi-bit storage in a conventional Flash memory cell.
In accordance with an aspect of the invention, a memory transistor has two laterally separated floating gates over a channel. A control gate that overlies the floating gates extends into a gap between the floating gates to directly modulate a central channel portion between the floating gates. The memory transistor can store separate data values as charge on the separate floating gates. The threshold voltage of the memory transistor depends on the charge stored on the floating gates and the direction of the channel current. Since the amount of charge that can be stored on each floating gate is relatively large compared to charge that can be trapped in a gate insulator, the amounts of stored charge and the threshold voltages of the dual-floating-gate memory transistor can be controlled more precisely than is possible in some known memory devices that store data as locally trapped charge. The control gate directly modulating the central channel region shuts off the current through unselected memory transistors, which permits xe2x80x9cover-erasingxe2x80x9d the floating gates to extend the usable threshold voltage range for storing data. The improved control of the threshold voltage and the larger available threshold voltage range facilitates reliable storage of multiple levels or multiple bits of data in each floating gate.
In accordance with a further aspect of the invention, the memory transistor having laterally separated floating gates uses holes in the floating gates to define the charge states representing data values. Charge states arising from holes on a floating gate are known to provide better data stability. The holes cause channel regions under the floating gate to have low or negative threshold voltages, while the central channel region, which the control gate modules, has a positive threshold voltage. Accordingly, the memory transistor is off when the control gate is grounded, but a read operation that biases the control gate to a level sufficient for charge inversion in the central channel region can compare the amount of current through a memory transistor to a reference current to determine a stored data value.
One specific embodiment of the invention is a device containing an array of memory transistors. Each memory transistor includes: a first source/drain region, a second source/drain region, and a channel in a substrate; a first floating gate overlying a first end of the channel adjacent the first source/drain region; a second floating gate overlying a second end of the channel adjacent the second source/drain region; and a control gate overlying the first and second floating gates and extending into the gap between the first and second floating gates. The first and second source/drain regions can extend under part of the first and second floating gates, respectively, to reduce the effective channel lengths under the first and second floating gates and improve the selectivity and precision of writing and reading stored data values associated with the floating gates.
In contactless, virtual ground architecture, the array includes multiple banks. Each bank includes diffused lines in the substrate, and each column of the memory transistors in the bank corresponds to and connects to an adjacent pair of the diffused lines. A first of the corresponding diffused lines electrically connects the first source/drain regions of the memory transistor in the row, and a second of the corresponding diffused lines electrically connects the second source/drain regions of the memory transistor in the row. Word lines overlie and connect to or form the control gates for the memory transistors in corresponding rows of the array.
Metal column lines overlie the banks and connect to the diffused lines through bank select devices. In particular, first bank select cells connect to respective column lines, and each first bank select cell is between the connected column line and a corresponding adjacent pair of the diffused lines. Second bank select cells also connect to the column lines with each second bank select cell being between the connected column line and a corresponding adjacent pair of the diffused lines. The first and second bank select cells connect to opposite ends of the diffused lines in the bank, and the adjacent pairs of diffused lines corresponding to the second bank select cells are offset relative to the adjacent pairs of diffused lines corresponding to the first bank select cells. With this configuration, the numbers of the column lines, the diffused lines, and the floating gates are in respective proportions N, 2Nxe2x88x921, and 4(Nxe2x88x921). The metal column lines, which connect to peripheral circuits, have a pitch that is wide compared to the pitch of metal lines in a conventional contactless Flash memory. The wider pitch provides additional area for layout of pitch-sensitive array supporting circuits and reduces capacitive coupling between metal column lines.
Another embodiment of the invention is an erase operation for a memory transistor having the above-described structure. The erase operation includes biasing the control gate and a well containing the memory transistor at respective negative and positive voltages that are sufficient to induce charge tunneling between the well and the first and second floating gates. The biasing of the control gate and the well is maintained to remove any excess electrons from the first and second floating gates and can be continued to over-erase the first and second floating gates. As a result, the first and second floating gates can have an excess of holes that gives the underlying channel regions negative threshold voltages and/or operation in depletion mode. The lower threshold voltage of the erased states for the memory transistors provides a wider threshold voltage range for analog or multi-bit data storage. High threshold voltages are not needed for data storage, which improves data retention, reduces cell disturb, and may avoid the need for word line boost circuits that can slow the biasing of word lines during random-access read operations.
Another embodiment of the invention is a write operation for a memory transistor such as described above. The write operation includes biasing the control gate, the first source/drain region, and the second source/drain region at a first programming voltage, ground, and a second programming voltage, respectively. The first and second programming voltages respectively on the control gate and the second source/drain region induce channel hot electron injection that injects electrons into the second floating gate without changing the charge on the first floating gate. The write operation can further include biasing the control gate, the first source/drain region, and the second source/drain region at the first programming voltage, the second programming voltage, and ground. The first and second programming voltages respectively on the control gate and the first source/drain region induce channel hot electron injection that injects electrons into the first floating gate without changing the charge on the second floating gate. The write operation can store a binary, analog, or multi-bit value on a floating gate by stopping the write operation when the floating gate reaches a charge state representing the value to be stored.
A series of verify operations can test whether a write operation has reached a target state corresponding to the value being stored. One verify operation biases the control gate at a first read voltage, grounds the second source/drain region, biases the first source/drain region at a second read voltage; and compares current through the memory transistor to a reference current associated with the multi-bit value. The first read voltage, which is applied to the control gate, is typically higher than the upper boundary of the threshold voltage range used to store data, which causes the memory transistor to be conductive regardless of the charge states of the floating gates. The write operation ends in response to the comparison indicating that the current through the memory transistor corresponds to a level associated with the value being written. An alternative verify operation can bias the control gate at the target threshold voltage for the memory transistor and then sense whether the memory transistor conducts.
Yet another embodiment of the invention is a read operation for a memory transistor having the structure described above. To read a data value associated with the first floating gate, the read operation includes: biasing the control gate at a first read voltage (typically higher than the highest threshold voltage used for data storage); grounding the first source/drain region; biasing the second source/drain region at a second read voltage; comparing a channel current of the memory transistor to one or more reference currents associated with stored values; and using results of the comparisons to determine a first stored value, which is associated with the first floating gate. To read a data value associated with the second floating gate, the read operation includes: biasing the control gate at the first voltage; grounding the second source/drain region; biasing the first source/drain region at the second voltage; comparing the channel current of the memory transistor to the one or more reference currents; and using results of these comparisons to determine a second stored value, which is associated with the second floating gate. The one or more reference currents can be a single reference current for storage of one bit or analog value per floating gate or multiple reference currents respectively corresponding to multi-bit stored values.
Yet another embodiment of the invention is a method for manufacturing a memory device. The method includes: forming a first source/drain region, a second source/drain/region, and a channel in a substrate, wherein the channel extends from the first source/drain region to the second source/drain region; forming a first floating gate overlying and insulated from a first portion of the channel adjacent the first source/drain region; forming a second floating gate overlying and insulated from a second portion of the channel adjacent the second source/drain region, wherein a gap between the second floating gate and the first floating gate overlies a central portion of the channel between the first and second portions of the channel; and forming a control gate overlying and insulated from the first and second floating gates, the control gate extending into the gap between the first and second floating gates and modulating the central portion of the channel.
The first and second source/drain regions can be formed before the first and second floating gates so that the first and second source/drain regions underlie significant portions of the first and second floating gates. Alternatively, the first and second source/drain regions can be formed by implanting impurities into the substrate using the first and second floating gates to at least partially define boundaries of implanted areas and then oxidizing the implanted regions at high temperature to cause the implanted regions to diffuse laterally under the first and second floating gates and to form oxide regions over the first and second source/drain regions. The first and second floating gates can also control implantation steps that adjust a threshold voltage of the central region relative to threshold voltages of the first and second portions of the channel.